9608_s21_qp_13
A paper of Computer Science, 9608
Questions:
9
Year:
2021
Paper:
1
Variant:
3

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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. DEC Subtract 1 from the contents of the register (ACC or . JMP Jump to the given address. CMP Compare the contents of ACC with the contents of . JPE Following a compare instruction, jump to if the compare was True. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The current contents of the main memory and selected values from the ASCII character set are: Address Instruction ASCII code table (selected codes only) LDR #2 ASCII code Character LDX 180 $ CMP #0 ( JPE 82 ) OUT + DEC IX E JMP 76 F END G … Complete a trace table for the execution of the program. Instruction address IX ACC Memory address Output Identify two modes of addressing that are not used in the assembly language program given. Each instruction in the assembly language program is encoded in 16 bits (8-bit op code followed by an 8-bit operand). The instruction LDX 234 has the operand 234. Convert the operand 234 into 8-bit binary. Convert the denary value 234 into hexadecimal. The contents of memory address 190 represent a two’s complement binary integer. Address Convert the value in memory address 190 into denary. The fetch-execute (FE) cycle is shown in register transfer notation. Complete the FE cycle using register transfer notation. ← [PC] PC ← + 1 MDR ← [[MAR]] ← [MDR]
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