9618_w21_qp_12
A paper of Computer Science, 9618
Questions:
8
Year:
2021
Paper:
1
Variant:
2

Login to start this paper & get access to powerful tools

3
4
5
6
A shop sells plants to customers. The shop manager has a relational database to keep track of the sales. The database, PLANTSALES, has the following structure: PLANT(PlantName, QuantityInStock, Cost) CUSTOMER(CustomerID, FirstName, LastName, Address, Email) PURCHASE(PurchaseID, CustomerID) PURCHASE_ITEM(PurchaseID, PlantName, Quantity) The database is normalised. The table lists the following three stages of normalisation: • The first stage is from a database that is not normalised (0NF) to First Normal Form (1NF). • The second stage is from 1NF to Second Normal Form (2NF). • The third stage is from 2NF to Third Normal Form (3NF). Tick () one box in each row to identify the appropriate stage for each task. Task Normalisation stage 0NF to 1NF 1NF to 2NF 2NF to 3NF Remove any partial key dependencies Remove any repeating groups of attributes Remove any non-key dependencies Draw an entity-relationship (E-R) diagram for the database PLANTSALES. PLANT PURCHASE_ITEM PURCHASE CUSTOMER The shop manager uses a Database Management System (DBMS). Describe the purpose and contents of the data dictionary in the DBMS. The shop manager uses both Data Definition Language (DDL) and Data Manipulation Language (DML) statements to create and search the database. Complete the DML statements to return the total number of items purchased with the purchase ID of 3011A. SELECT SUM( ) FROM WHERE = ; Write DDL statements to include a field in the table PURCHASE to store the date of the order.
7
8
The Von Neumann model for a computer system uses registers. Describe the role of the following special purpose registers in the fetch-execute (F-E) cycle. Memory Address Register (MAR) Memory Data Register (MDR) Another special purpose register is the Index Register. Identify one other special purpose register used in the Von Neumann model for a computer system. The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC STO Store the contents of ACC at the given address INC Add 1 to the contents of the register (ACC or CMP Compare the contents of ACC with the contents of JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address IN Key in a character and store its ASCII value in ACC OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 The current contents of main memory are shown: Address Data In the following table, each row shows the current contents of the ACC in binary and the instruction that will be performed on those contents. Complete the table by writing the new contents of the ACC after the execution of each instruction. Current contents of the ACC Instruction New contents of the ACC XOR 101 AND 104 LSL #4 OR 102 The following table contains five assembly language instruction groups. Write an appropriate assembly language instruction for each instruction group, using the given instruction set. The first one has been completed for you. Instruction Group Instruction Data movement LDM #2 Input and output of data Arithmetic operations Unconditional and conditional instructions Compare instructions The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing. Identify and describe one additional mode of addressing. Mode of addressing Description