Three descriptions and two types of processor are shown below. Draw a line to connect each description to the appropriate type of processor. Description Type of processor Makes extensive use of general purpose registers RISC Many addressing modes are available CISC Has a simplified set of instructions In a RISC processor three instructions (A followed by B, followed by C) are processed using pipelining. The following table shows the five stages that occur when instructions are fetched and executed. The ‘A’ in the table indicates that instruction A has been fetched in time interval 1. Complete the table to show the time interval in which each stage of each instruction (A, B, C) is carried out. Time interval Stage Fetch instruction A Decode instruction Execute instruction Access operand in memory Write result to register The completed table shows how pipelining allows instructions to be carried out more rapidly. Each time interval represents one clock cycle. Calculate how many clock cycles are saved by the use of pipelining in the above example. Show your working.

9608_w15_qp_31

THEORY

2015

Paper 3, Variant 1

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Three descriptions and two types of processor are shown below. Draw a line to connect each description to the appropriate type of processor. Description Type of processor Makes extensive use of general purpose registers RISC Many addressing modes are available CISC Has a simplified set of instructions In a RISC processor three instructions (A followed by B, followed by C) are processed using pipelining. The following table shows the five stages that occur when instructions are fetched and executed. The ‘A’ in the table indicates that instruction A has been fetched in time interval 1. Complete the table to show the time interval in which each stage of each instruction (A, B, C) is carried out. Time interval Stage Fetch instruction A Decode instruction Execute instruction Access operand in memory Write result to register The completed table shows how pipelining allows instructions to be carried out more rapidly. Each time interval represents one clock cycle. Calculate how many clock cycles are saved by the use of pipelining in the above example. Show your working.

9608_w15_qp_33

THEORY

2015

Paper 3, Variant 3

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. CMP Compare contents of ACC with contents of JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The diagram shows the contents of the main memory: Main memory 0110 0100 0111 1100 1001 0111 0111 0011 1001 0000 0011 1111 0000 1110 1110 1000 1000 1110 1100 0010 : : 1011 0101 Show the contents of the Accumulator after execution of the instruction: LDD 802 Accumulator: Show the contents of the Accumulator after execution of the instruction: LDX 800 Index Register: Accumulator: Explain how you arrived at your answer. Complete the trace table below for the following assembly language program. This program contains denary values. LDD 800 ADD 801 STO 802 LDD 803 CMP 802 JPE 107 JPN 110 STO 802 OUT JMP 112 LDD 801 OUT END : : Selected values from the ASCII character set: ASCII code Character ( P Z d Trace table: ACC Memory address OUTPUT There is a redundant instruction in the code in part . State the address of this instruction. The program used the ASCII coding system for character codes. An alternative coding system is Unicode. Give two disadvantages of using ASCII code. Describe how Unicode is designed to overcome the disadvantages of ASCII.

9608_w16_qp_11

THEORY

2016

Paper 1, Variant 1

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The table shows assembly language instructions for a processor that has one general purpose register, the Accumulator (ACC) and an index register (. Instruction Explanation Op Code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDX Index addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC. STO Store the contents of ACC at the given address. INC Add 1 to contents of the register (ACC or . ADD Add the contents of the given address to the ACC. END Return control to the operating system. The diagram shows the contents of a section of main memory: Main memory 0000 0010 1001 0011 0111 0011 0110 1011 0111 1110 1011 0001 0110 1000 0100 1011 … 1001 1110 Show the contents of the Accumulator after the execution of the instruction: LDD 102 ACC: Show the contents of the Accumulator after the execution of the instruction: LDX 101 IX: ACC: Explain how you arrived at your answer. Show the contents of the Accumulator after the execution of the instruction: LDI 103 ACC: Explain how you arrived at your answer. Complete the trace table below for the following assembly language program. LDD 810 INC ACC STO 812 LDD 811 ADD 812 STO 813 END … Trace table: ACC Memory address

9608_w16_qp_12

THEORY

2016

Paper 1, Variant 2

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. CMP Compare contents of ACC with contents of JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The diagram shows the contents of the main memory: Main memory 0110 0100 0111 1100 1001 0111 0111 0011 1001 0000 0011 1111 0000 1110 1110 1000 1000 1110 1100 0010 : : 1011 0101 Show the contents of the Accumulator after execution of the instruction: LDD 802 Accumulator: Show the contents of the Accumulator after execution of the instruction: LDX 800 Index Register: Accumulator: Explain how you arrived at your answer. Complete the trace table below for the following assembly language program. This program contains denary values. LDD 800 ADD 801 STO 802 LDD 803 CMP 802 JPE 107 JPN 110 STO 802 OUT JMP 112 LDD 801 OUT END : : Selected values from the ASCII character set: ASCII code Character ( P Z d Trace table: ACC Memory address OUTPUT There is a redundant instruction in the code in part . State the address of this instruction. The program used the ASCII coding system for character codes. An alternative coding system is Unicode. Give two disadvantages of using ASCII code. Describe how Unicode is designed to overcome the disadvantages of ASCII.

9608_w16_qp_13

THEORY

2016

Paper 1, Variant 3

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The following diagram shows four descriptions and two types of processor. Draw lines to connect each description to the appropriate type of processor. Description Type of processor It has a simplified set of instructions. Emphasis is on the hardware rather than the software. CISC It makes extensive use of general purpose registers. RISC Many instruction formats are available. In a RISC processor, instructions are processed using pipelining. Explain what is meant by pipelining. The following table shows the five stages that occur when instructions are fetched and executed. The table also shows a number of time intervals. Two instructions, D followed by E, are fetched and executed. The ‘E’ in the incomplete table shows that instruction E has been fetched in time interval 2. Complete each row of the table. Time interval Stage Fetch instruction E Read registers and decode instruction Execute instruction Access operand in memory Write result to register The instruction set for a RISC processor that allows pipelining includes the following instruction. Instruction Explanation Op code Operands ADD , , Add the integers in registers op1 and op2. Place the result in register dest. A program contains the following three instructions. ADD r3, r2, r1 ADD r5, r4, r3 ADD r10, r9, r8 Explain why pipelining fails for the first two instructions. The instructions were produced by a compiler after translation of a high-level language program. The compiler is not capable of code optimisation. State how the code from the compiler could have been optimised to overcome the problem in part .

9608_w17_qp_32

THEORY

2017

Paper 3, Variant 2

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an index register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. State what is meant by direct addressing and indirect addressing. Direct addressing Indirect addressing Explain how the instruction ADD 20 can be interpreted as either direct or indirect addressing. Direct addressing Indirect addressing The assembly language instructions in the following table use either symbolic addressing or absolute addressing. Tick (3) one box in each row to indicate whether the instruction uses symbolic or absolute addressing. Instruction Symbolic Absolute ADD 90 CMP found STO 20 The current contents of a general purpose register (are: X The contents of X represent an unsigned binary integer. Convert the value in X into denary. The contents of X represent an unsigned binary integer. Convert the value in X into hexadecimal. The contents of X represent a two’s complement binary integer. Convert the value in X into denary. The current contents of the main memory, Index Register (and selected values from the ASCII character set are provided with a copy of the instruction set. Address Instruction LDX 200 OUT STO 203 LDD 204 INC ACC STO 204 INC IX LDX 200 CMP 203 JPN 81 OUT LDD 204 CMP 205 JPN 74 END … IX ASCII code table (selected codes only) ASCII code Character ? ! “ * $ & % / Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. Instruction set

9608_w18_qp_11

THEORY

2018

Paper 1, Variant 1

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The following table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following compare instruction, jump to if the compare was True. JPN Following compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. State what is meant by absolute addressing and symbolic addressing. Absolute addressing Symbolic addressing Give an example of an ADD instruction using both absolute addressing and symbolic addressing. Absolute addressing Symbolic addressing State what is meant by indexed addressing and immediate addressing. Indexed addressing Immediate addressing Give an example of an instruction that uses: Indexed addressing Immediate addressing The current contents of a general purpose register (are: X The contents of X represent an unsigned binary integer. Convert the value in X into denary. The contents of X represent an unsigned binary integer. Convert the value in X into hexadecimal. The contents of X represent a two’s complement binary integer. Convert the value in X into denary. The current contents of the main memory, Index Register (and selected values from the ASCII character set are: Address Instruction ASCII code table (selected codes only) LDD 100 ASCII code Character CMP 104 / JPE 54 * LDX 100 - CMP 105 + JPN 47 ^ OUT = LDD 100 DEC ACC STO 100 INC IX JMP 41 END … IX This is a copy of the instruction set. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system.

9608_w18_qp_12

THEORY

2018

Paper 1, Variant 2

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The following table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following compare instruction, jump to if the compare was True. JPN Following compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. State what is meant by relative addressing and indexed addressing. Relative addressing Indexed addressing The current contents of a general purpose register (are: X The contents of X represent an unsigned binary integer. Convert the value in X into denary. The contents of X represent an unsigned binary integer. Convert the value in X into hexadecimal. The contents of X represent a two’s complement binary integer. Convert the value in X into denary. Show the result on the general purpose register (after the following instruction is run. INC X The current contents of the main memory, Index Register (and selected values from the ASCII character set are provided with a copy of the instruction set. Instruction set Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. Address Instruction LDD 96 CMP 97 JPE 32 LDX 86 CMP 98 JPN 27 OUT LDD 96 INC ACC STO 96 INC IX JMP 21 END … IX ASCII code table (selected codes only) ASCII code Character = & ( )

9608_w18_qp_13

THEORY

2018

Paper 1, Variant 3

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The fetch-execute (FE) cycle uses special purpose registers. The stages in the FE cycle are shown in register transfer notation. MAR PC PC + 1 [ ] The steps shown in part are incomplete. Write the missing register names in the spaces in part . The third instruction [ ] has double brackets. State the purpose of the double brackets. One stage of the FE cycle includes checking for interrupts. State what is meant by an interrupt. There are two types of RAM: dynamic RAM (DRAM) and static RAM (SRAM). The following table shows five statements about DRAM and SRAM. Tick (✓) one box in each row to indicate whether the statement applies to DRAM or SRAM. Statement DRAM SRAM Does not need to be refreshed as the circuit holds the data while the power supply is on Mainly used in cache memory of processors where speed is important Has less complex circuitry Requires higher power consumption under low levels of access, which is significant when used in battery-powered devices Requires data to be refreshed occasionally so it retains the data

9608_w18_qp_13

THEORY

2018

Paper 1, Variant 3

View

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