9618_w21_qp_11
A paper of Computer Science, 9618
Questions:
8
Year:
2021
Paper:
1
Variant:
1

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There are two errors in the following register transfer notation for the fetch‑execute cycle. MAR [PC] PC [PC] − 1 MDR [MAR] CIR [MDR] Complete the following table by: • identifying the line number of each error • describing the error • writing the correct statement. Line number Description of the error Correct statement The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC STO Store the contents of ACC at the given address INC Add 1 to the contents of the register (ACC or CMP Compare the contents of ACC with the contents of JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address IN Key in a character and store its ASCII value in ACC OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The current contents of main memory are shown: Address Data
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