4.2. Assembly Language
A subsection of Computer Science, 9618, through 4. Processor Fundamentals
Listing 7 of 7 questions
The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC STO Store contents of ACC at the given address ADD Add the contents of the given address to the ACC INC Add 1 to the contents of the register (ACC or DEC Subtract 1 from the contents of the register (ACC or CMP Compare the contents of ACC with the contents of JPE Following a compare instruction, jump to if the compare was True JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address IN Key in a character and store its ASCII value in ACC OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system # denotes a denary number, e.g. #123 The current contents of the main memory and selected values from the ASCII character set are: Address Instruction ASCII code table (selected codes only) IN ASCII code Character CMP 100 A JPE 80 B CMP 101 C JPE 76 D JMP 80 LDD 102 INC ACC STO 102 JMP 70 LDD 102 DEC ACC STO 102 JMP 70 … Complete the trace table for the program currently in main memory when the following characters are input: A D Do not trace the program any further when the third input is required. Instruction address ACC Memory address Some bit manipulation instructions are shown in the table: Instruction Explanation Opcode Operand AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of can be an absolute address or a symbolic address # denotes a denary number, e.g. #123 The contents of the memory address 300 are shown: Bit Number The contents of memory address 300 represent an unsigned binary integer. Write the denary value of the unsigned binary integer in memory address 300. An assembly language program needs to test if bit number 2 in memory address 300 is a 1. Complete the assembly language instruction to perform this test. #4 An assembly language program needs to set bit numbers 4, 5, 6 and 7 to 0, but keep bits 0 to 3 with their existing values. Write the assembly language instruction to perform this action.
9618_s21_qp_12
THEORY
2021
Paper 1, Variant 2
The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the number n to IX STO Store the contents of ACC at the given address ADD Add the contents of the given address to the ACC ADD #n Add the denary number n to the ACC INC Add 1 to the contents of the register (ACC or JMP Jump to the given address CMP Compare the contents of ACC with the contents of CMI Indirect addressing. The address to be used is at the given address. Compare the contents of ACC with the contents of this second address JPE Following a compare instruction, jump to if the compare was True JPN Following a compare instruction, jump to if the compare was False END Return control to the operating system can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 Trace the program currently in memory using the trace table, stopping when line 90 is executed for a second time. Address Instruction LDR #0 LDX 110 CMI 102 JPE 91 CMP 103 JPN 84 ADD 101 STO 101 JMP 86 INC ACC STO 101 LDD 100 INC ACC STO 100 INC IX JMP 76 END … … Instruction address ACC IX Memory address The following table shows another part of the instruction set for the processor. Instruction Explanation Opcode Operand AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n XOR Bitwise XOR operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right-hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left-hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The contents of memory addresses 50 and 51 are shown: Memory address Data value The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. XOR B00011111 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. AND 50 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. LSL #3 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. OR 51 Write the register transfer notation for each of the stages in the fetch-execute cycle described in the table. Description Register transfer notation Copy the address of the next instruction into the Memory Address Register. Increment the Program Counter. Copy the contents of the Memory Data Register into the Current Instruction Register.
9618_w22_qp_12
THEORY
2022
Paper 1, Variant 2
The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the number n to IX MOV Moves the contents of the accumulator to the given register (STO Store contents of ACC at the given address ADD Add the contents of the given address to the ACC ADD #n Add the denary number n to the ACC SUB #n Subtract the denary number n from the ACC INC Add 1 to the contents of the register (ACC or JMP Jump to the given address CMP #n Compare the contents of ACC with number n CMI Indirect addressing. The address to be used is at the given address. Compare the contents of ACC with the contents of this second address JPE Following a compare instruction, jump to if the compare was True JPN Following a compare instruction, jump to if the compare was False OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system can be an absolute or a symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The current contents of main memory and selected values from the ASCII character set are given. Trace the program currently in memory using the trace table. Address Instruction LDR #0 LDD 100 CMP #2 JPE 91 LDX 110 SUB #32 CMP #65 JPN 86 LDM #1 ADD 101 STO 101 LDM #1 ADD 100 STO 100 INC IX JMP 76 LDD 101 ADD #48 OUT END … … ASCII value Character A B C D Instruction address ACC IX Memory address Output Explain the purpose of relative addressing in an assembly language program. The following table shows another part of the instruction set for the processor. Instruction Explanation Opcode Operand AND #n Bitwise AND operation of the contents of ACC with the operand AND Bn Bitwise AND operation of the contents of ACC with the binary number n AND Bitwise AND operation of the contents of ACC with the contents of XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bn Bitwise OR operation of the contents of ACC with the binary number n OR Bitwise OR operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right-hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left-hand end can be an absolute or a symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. AND B01001100 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. OR B01001111 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. LSR #2 One instruction group is data movement. Give the name of one other instruction group.
9618_w22_qp_13
THEORY
2022
Paper 1, Variant 3
9618_s22_qp_13
THEORY
2022
Paper 1, Variant 3
Questions Discovered
7