9618_w22_qp_12
A paper of Computer Science, 9618
Questions:
10
Year:
2022
Paper:
1
Variant:
2

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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the number n to IX STO Store the contents of ACC at the given address ADD Add the contents of the given address to the ACC ADD #n Add the denary number n to the ACC INC Add 1 to the contents of the register (ACC or JMP Jump to the given address CMP Compare the contents of ACC with the contents of CMI Indirect addressing. The address to be used is at the given address. Compare the contents of ACC with the contents of this second address JPE Following a compare instruction, jump to if the compare was True JPN Following a compare instruction, jump to if the compare was False END Return control to the operating system can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 Trace the program currently in memory using the trace table, stopping when line 90 is executed for a second time. Address Instruction LDR #0 LDX 110 CMI 102 JPE 91 CMP 103 JPN 84 ADD 101 STO 101 JMP 86 INC ACC STO 101 LDD 100 INC ACC STO 100 INC IX JMP 76 END … … Instruction address ACC IX Memory address The following table shows another part of the instruction set for the processor. Instruction Explanation Opcode Operand AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n XOR Bitwise XOR operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right-hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left-hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The contents of memory addresses 50 and 51 are shown: Memory address Data value The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. XOR B00011111 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. AND 50 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. LSL #3 The current contents of the ACC are: Show the contents of the ACC after the execution of the following instruction. OR 51 Write the register transfer notation for each of the stages in the fetch-execute cycle described in the table. Description Register transfer notation Copy the address of the next instruction into the Memory Address Register. Increment the Program Counter. Copy the contents of the Memory Data Register into the Current Instruction Register.
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