Complete the following sentences that describe parts of a processor in a Von Neumann model for a computer system. There are buses that transfer data between components in a computer system. The width of the determines the number of directly accessible memory locations. The sends signals on the to direct the operation of system components. pulses are used to synchronise the components on the motherboard. Describe the stages of the fetch-execute (F-E) cycle.

9608_w21_qp_11

THEORY

2021

Paper 1, Variant 1

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Explain how the width of the data bus and system clock speed affect the performance of a computer system. Width of the data bus Clock speed Most computers use Universal Serial Bus (USB) ports to allow the attachment of devices. Describe two benefits of using USB ports. The table shows six stages in the von Neumann fetch-execute cycle. Put the stages into the correct sequence by writing the numbers 1 to 6 in the right hand column. Description of stage Sequence number the instruction is copied from the Memory Data Register (MDR) and placed in the Current Instruction Register (CIR) the instruction is executed the instruction is decoded the address contained in the Program Counter (PC) is copied to the Memory Address Register (MAR) the value in the Program Counter (PC) is incremented so that it points to the next instruction to be fetched the instruction is copied from the memory location contained in the Memory Address Register (MAR) and is placed in the Memory Data Register (MDR)

9608_s15_qp_11

THEORY

2015

Paper 1, Variant 1

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Explain how the width of the data bus and system clock speed affect the performance of a computer system. Width of the data bus Clock speed Most computers use Universal Serial Bus (USB) ports to allow the attachment of devices. Describe two benefits of using USB ports. The table shows six stages in the von Neumann fetch-execute cycle. Put the stages into the correct sequence by writing the numbers 1 to 6 in the right hand column. Description of stage Sequence number the instruction is copied from the Memory Data Register (MDR) and placed in the Current Instruction Register (CIR) the instruction is executed the instruction is decoded the address contained in the Program Counter (PC) is copied to the Memory Address Register (MAR) the value in the Program Counter (PC) is incremented so that it points to the next instruction to be fetched the instruction is copied from the memory location contained in the Memory Address Register (MAR) and is placed in the Memory Data Register (MDR)

9608_s15_qp_12

THEORY

2015

Paper 1, Variant 2

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC). Instruction Explanation Op code Operand LDD Direct addressing. Load contents of given address to ACC STO Store the contents of ACC at the given address LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC INC Add 1 to contents of the register (ACC) JMP Jump to the given address END Return control to operating system The diagram shows the contents of the memory. Main memory 0 0 0 0 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0 0 Show the contents of the Accumulator after execution of the instruction: LDD 121 Accumulator: Show the contents of the Accumulator after execution of the instruction: LDI 124 Accumulator: Explain how you arrived at your answer. Show the contents of the Accumulator after execution of the instruction: LDX 120 Index Register: Accumulator: Explain how you arrived at your answer. Trace the assembly language program using the trace table. LDD INC STO LDI INC STO END Trace table: Accumulator Memory address

9608_s15_qp_13

THEORY

2015

Paper 1, Variant 3

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Describe how special purpose registers are used in the fetch stage of the fetch-execute cycle. Use the statements A, B, C and D to complete the description of how the fetch-execute cycle handles an interrupt. A the address of the Interrupt Service Routine (ISR) is loaded to the Program Counter (PC). B the processor checks if there is an interrupt. C when the ISR completes, the processor restores the register contents. D the register contents are saved. At the end of the cycle for the current instruction . If the interrupt flag is set, , and . The interrupted program continues its execution.

9608_s16_qp_11

THEORY

2016

Paper 1, Variant 1

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an index register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The diagram shows the current contents of a section of main memory and the index register: 0011 0010 0101 1101 0000 0100 1111 1001 0101 0101 1101 1111 0000 1101 0100 1101 0100 0101 0100 0011 0110 1001 Index register: 0 Show the contents of the Accumulator after the execution of the instruction: LDX 60 Accumulator: Show how you obtained your answer. Show the contents of the index register after the execution of the instruction: DEC IX Index register: Complete the trace table on the opposite page for the following assembly language program. LDD 100 ADD 102 STO 103 LDX 100 ADD 100 CMP 101 JPE 58 JPN 59 OUT INC IX LDX 98 ADD 101 OUT END IX (Index Register) Selected values from the ASCII character set: ASCII Code Character v w x y z { | }

9608_s16_qp_11

THEORY

2016

Paper 1, Variant 1

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Describe how special purpose registers are used in the fetch stage of the fetch-execute cycle. Use the statements A, B, C and D to complete the description of how the fetch-execute cycle handles an interrupt. A the address of the Interrupt Service Routine (ISR) is loaded to the Program Counter (PC). B the processor checks if there is an interrupt. C when the ISR completes, the processor restores the register contents. D the register contents are saved. At the end of the cycle for the current instruction . If the interrupt flag is set, , and . The interrupted program continues its execution.

9608_s16_qp_12

THEORY

2016

Paper 1, Variant 2

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an index register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The diagram shows the current contents of a section of main memory and the index register: 0011 0010 0101 1101 0000 0100 1111 1001 0101 0101 1101 1111 0000 1101 0100 1101 0100 0101 0100 0011 0110 1001 Index register: 0 Show the contents of the Accumulator after the execution of the instruction: LDX 60 Accumulator: Show how you obtained your answer. Show the contents of the index register after the execution of the instruction: DEC IX Index register: Complete the trace table on the opposite page for the following assembly language program. LDD 100 ADD 102 STO 103 LDX 100 ADD 100 CMP 101 JPE 58 JPN 59 OUT INC IX LDX 98 ADD 101 OUT END IX (Index Register) Selected values from the ASCII character set: ASCII Code Character v w x y z { | }

9608_s16_qp_12

THEORY

2016

Paper 1, Variant 2

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The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an index register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The diagram shows the contents of the index register: Index register: Show the contents of the index register after the execution of the instruction: INC IX Index register: Complete the trace table on the opposite page for the following assembly language program. LDX 90 DEC ACC STO 90 INC IX LDX 90 DEC ACC CMP 90 JPE 29 JPN 31 ADD 90 OUT ADD 93 STO 93 OUT END : : IX Selected values from the ASCII character set: ASCII Code Character A B C D E F G H

9608_s16_qp_13

THEORY

2016

Paper 1, Variant 3

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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand Op code LDM #n 0000 0001 Immediate addressing. Load the denary number n to ACC. LDD 0000 0010 Direct addressing. Load the contents of the location at the given address to ACC. LDI 0000 0101 Indirect addressing. At the given address is the address to be used. Load the contents of this second address to ACC. LDX 0000 0110 Indexed addressing. Form the address from + the contents of the Index Register (. Copy the contents of this calculated address to ACC. LDR #n 0000 0111 Immediate addressing. Load number n to IX. STO 0000 1111 Store the contents of ACC at the given address. The following diagram shows the contents of a section of main memory and the Index Register (. Show the contents of the Accumulator (ACC) after each instruction is executed. IX LDM #500 ACC LDD 500 ACC LDX 500 ACC LDI 500 ACC Address Main Memory contents Each machine code instruction is encoded as 16-bits (8-bit op code followed by an 8-bit operand). Write the machine code for the following instructions: LDM #17 LDX #97 Using an 8-bit operand, state the maximum number of memory locations, in denary, that can be directly addressed. Computer scientists often write binary representations in hexadecimal. Write the hexadecimal representation for this instruction: A second instruction has been written in hexadecimal as: 05 3F Write the equivalent assembly language instruction, with the operand in denary.

9608_s17_qp_11

THEORY

2017

Paper 1, Variant 1

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