1.4. Processor fundamentals
A subsection of Computer Science, 9608, through 1. Theory Fundamentals
Listing 10 of 63 questions
The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand Op code LDD 0001 0011 Direct addressing. Load the contents of the location at the given address to the Accumulator (ACC). LDI 0001 0100 Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC. LDX 0001 0101 Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDM #n 0001 0010 Immediate addressing. Load the denary number n to ACC. LDR #n 0001 0110 Immediate addressing. Load denary number n to the Index Register (. STO 0000 0111 Store the contents of ACC at the given address. The following diagram shows the contents of a section of main memory and the Index Register (. Show the contents of the Accumulator (ACC) after each instruction is executed. IX LDD 355 ACC LDM #355 ACC LDX 351 ACC LDI 355 ACC Address Main memory contents Each machine code instruction is encoded as 16 bits (8-bit op code followed by an 8-bit operand). Write the machine code for these instructions: LDM #67 LDX #7 Computer scientists often write binary representations in hexadecimal. Write the hexadecimal representation for the following instruction. A second instruction has been written in hexadecimal as: 16 4D Write the assembly language for this instruction with the operand in denary.
9608_s17_qp_12
THEORY
2017
Paper 1, Variant 2
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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand Op code LDM #n 0000 0001 Immediate addressing. Load the denary number n to ACC. LDD 0000 0010 Direct addressing. Load the contents of the location at the given address to ACC. LDI 0000 0101 Indirect addressing. At the given address is the address to be used. Load the contents of this second address to ACC. LDX 0000 0110 Indexed addressing. Form the address from + the contents of the Index Register (. Copy the contents of this calculated address to ACC. LDR #n 0000 0111 Immediate addressing. Load number n to IX. STO 0000 1111 Store the contents of ACC at the given address. The following diagram shows the contents of a section of main memory and the Index Register (. Show the contents of the Accumulator (ACC) after each instruction is executed. IX LDM #500 ACC LDD 500 ACC LDX 500 ACC LDI 500 ACC Address Main Memory contents Each machine code instruction is encoded as 16-bits (8-bit op code followed by an 8-bit operand). Write the machine code for the following instructions: LDM #17 LDX #97 Using an 8-bit operand, state the maximum number of memory locations, in denary, that can be directly addressed. Computer scientists often write binary representations in hexadecimal. Write the hexadecimal representation for this instruction: A second instruction has been written in hexadecimal as: 05 3F Write the equivalent assembly language instruction, with the operand in denary.
9608_s17_qp_13
THEORY
2017
Paper 1, Variant 3
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The fetch-execute cycle is shown in register transfer notation. MAR PC - 1 MDR CIR There are three errors in the fetch-execute cycle shown. Identify the line number of each error and give the correction. Line number Correction Line number Correction Line number Correction A processor’s instruction set can be grouped according to their function. For example, one group is the input and output of data. Identify two other groups of instructions. The following table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDM #n Immediate addressing. Load the denary number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the denary number n to IX STO Store contents of ACC at the given address ADD Add the contents of the given address to ACC INC Add 1 to the contents of the register (ACC or CMP #n Compare contents of ACC with denary number n JPE Following a compare instruction, jump to if the compare was True JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system The current contents of the main memory, Index Register (and selected values from the ASCII character set are: Address Instruction LDM #0 STO 401 LDX 300 CMP #0 JPE 62 ADD 400 OUT LDD 401 INC ACC STO 401 INC IX JMP 52 END … … IX ASCII code table (Selected codes only) ASCII code Character A B C D E The ASCII character code for ‘A’ is 65 in denary. Convert the denary ASCII character code for ‘A’ into 8-bit binary. Convert the denary ASCII character code for ‘A’ into hexadecimal. The Unicode character code for ‘G’ is 0047 in hexadecimal. State, in hexadecimal, the Unicode character code for ‘D’.
9608_s19_qp_12
THEORY
2019
Paper 1, Variant 2
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A processor has one general purpose register, the Accumulator (ACC), and an Index Register (. The table gives three assembly language instructions for loading data into the ACC. It also identifies the addressing mode used for each instruction. Instruction Addressing mode A LDM #193 Immediate B LDD 193 Direct C LDX 193 Indexed State the contents of the Accumulator after each of the instructions A, B and C are run. A B C Name two other addressing modes. The ACC is a general purpose register. The IX is a special purpose register. Identify two other special purpose registers used in the fetch-execute cycle and describe their role in the cycle. Register 1 Role Register 2 Role
9608_s20_qp_11
THEORY
2020
Paper 1, Variant 1
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The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the content of the location at the given address to ACC. LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC. DEC Subtract 1 from the contents of the register (ACC or . CMP Compare the contents of ACC with the contents of . JMP Jump to the given address. JPE Following a compare instruction, jump to if the compare was True. STO Store the contents of ACC at the given address. END Return control to the operating system. The current contents of the main memory are: Address Instruction LDD 200 CMP 201 JPE 106 DEC ACC STO 200 JMP 101 END … Trace the program currently in memory using the following trace table. Instruction address ACC Memory address The instruction in memory address 100 needs to be changed. It needs to use indirect addressing to load the contents of memory address 200. Give the new instruction to replace LDD 200. Each instruction in the assembly language program is encoded in 16 bits (8-bit op code followed by an 8-bit operand). The instruction CMP 201 has the operand 201. Convert the operand 201 into 8-bit binary. State the maximum number of op codes that can be represented using eight bits. The status register contains condition flags. Identify three condition flags that can be set in the status register.
9608_s21_qp_11
THEORY
2021
Paper 1, Variant 1
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The following diagram shows four register notations and seven descriptions. Draw one line from each register notation to its most appropriate description. Register notation Description MDR CIR MAR PC Holds the op code and operand of an instruction ready for it to be decoded Holds the address of the next instruction to be read Holds flags that are set when the Arithmetic and Logic Unit (ALU) executes instructions Holds data read from, or to be written to, memory Holds the current value in the Index Register Holds the address where data is to be written to or read from Holds the result of the last instruction executed by the ALU
9608_s21_qp_12
THEORY
2021
Paper 1, Variant 2
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The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC. STO Store the contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . JMP Jump to the given address. CMP Compare the contents of ACC with the contents of . JPE Following a compare instruction, jump to if the compare was True. END Return control to the operating system. The current contents of the main memory are: Address Instruction LDI 103 CMP 101 JPE 59 ADD 102 STO 102 LDD 100 INC ACC STO 100 JMP 51 ADD 102 STO 102 END … Trace the program currently in memory using the following trace table. Instruction address ACC Memory address The instruction in memory address 50 needs to be changed to use direct addressing to load the contents of the memory location at address 100. Give the new instruction to replace LDI 103. Each instruction in the assembly language program is encoded in 16 bits (8-bit op code followed by an 8-bit operand). The instruction JPE 59 has the operand 59. Convert the operand 59 into 8-bit binary. Convert the denary value 59 into hexadecimal. The assembly language program uses direct and indirect addressing. Identify two other modes of addressing used in an assembly language program.
9608_s21_qp_12
THEORY
2021
Paper 1, Variant 2
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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDX Indexed addressing. Form the address from + the contents of the index register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. DEC Subtract 1 from the contents of the register (ACC or . JMP Jump to the given address. CMP Compare the contents of ACC with the contents of . JPE Following a compare instruction, jump to if the compare was True. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The current contents of the main memory and selected values from the ASCII character set are: Address Instruction ASCII code table (selected codes only) LDR #2 ASCII code Character LDX 180 $ CMP #0 ( JPE 82 ) OUT + DEC IX E JMP 76 F END G … Complete a trace table for the execution of the program. Instruction address IX ACC Memory address Output Identify two modes of addressing that are not used in the assembly language program given. Each instruction in the assembly language program is encoded in 16 bits (8-bit op code followed by an 8-bit operand). The instruction LDX 234 has the operand 234. Convert the operand 234 into 8-bit binary. Convert the denary value 234 into hexadecimal. The contents of memory address 190 represent a two’s complement binary integer. Address Convert the value in memory address 190 into denary. The fetch-execute (FE) cycle is shown in register transfer notation. Complete the FE cycle using register transfer notation. ← PC ← + 1 MDR ← [] ←
9608_s21_qp_13
THEORY
2021
Paper 1, Variant 3
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Questions Discovered
63