1.4. Processor fundamentals
A subsection of Computer Science, 9608, through 1. Theory Fundamentals
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The following table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following compare instruction, jump to if the compare was True. JPN Following compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. State what is meant by absolute addressing and symbolic addressing. Absolute addressing Symbolic addressing Give an example of an ADD instruction using both absolute addressing and symbolic addressing. Absolute addressing Symbolic addressing State what is meant by indexed addressing and immediate addressing. Indexed addressing Immediate addressing Give an example of an instruction that uses: Indexed addressing Immediate addressing The current contents of a general purpose register (are: X The contents of X represent an unsigned binary integer. Convert the value in X into denary. The contents of X represent an unsigned binary integer. Convert the value in X into hexadecimal. The contents of X represent a two’s complement binary integer. Convert the value in X into denary. The current contents of the main memory, Index Register (and selected values from the ASCII character set are: Address Instruction ASCII code table (selected codes only) LDD 100 ASCII code Character CMP 104 / JPE 54 * LDX 100 - CMP 105 + JPN 47 ^ OUT = LDD 100 DEC ACC STO 100 INC IX JMP 41 END … IX This is a copy of the instruction set. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system.
9608_w18_qp_12
THEORY
2018
Paper 1, Variant 2
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The following table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC) and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following compare instruction, jump to if the compare was True. JPN Following compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. State what is meant by relative addressing and indexed addressing. Relative addressing Indexed addressing The current contents of a general purpose register (are: X The contents of X represent an unsigned binary integer. Convert the value in X into denary. The contents of X represent an unsigned binary integer. Convert the value in X into hexadecimal. The contents of X represent a two’s complement binary integer. Convert the value in X into denary. Show the result on the general purpose register (after the following instruction is run. INC X The current contents of the main memory, Index Register (and selected values from the ASCII character set are provided with a copy of the instruction set. Instruction set Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . DEC Subtract 1 from the contents of the register (ACC or . CMP Compare contents of ACC with contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to the screen the character whose ASCII value is stored in ACC. END Return control to the operating system. Address Instruction LDD 96 CMP 97 JPE 32 LDX 86 CMP 98 JPN 27 OUT LDD 96 INC ACC STO 96 INC IX JMP 21 END … IX ASCII code table (selected codes only) ASCII code Character = & ( )
9608_w18_qp_13
THEORY
2018
Paper 1, Variant 3
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The fetch-execute (FE) cycle uses special purpose registers. The stages in the FE cycle are shown in register transfer notation. MAR PC PC + 1 [ ] The steps shown in part are incomplete. Write the missing register names in the spaces in part . The third instruction [ ] has double brackets. State the purpose of the double brackets. One stage of the FE cycle includes checking for interrupts. State what is meant by an interrupt. There are two types of RAM: dynamic RAM (DRAM) and static RAM (SRAM). The following table shows five statements about DRAM and SRAM. Tick (✓) one box in each row to indicate whether the statement applies to DRAM or SRAM. Statement DRAM SRAM Does not need to be refreshed as the circuit holds the data while the power supply is on Mainly used in cache memory of processors where speed is important Has less complex circuitry Requires higher power consumption under low levels of access, which is significant when used in battery-powered devices Requires data to be refreshed occasionally so it retains the data
9608_w18_qp_13
THEORY
2018
Paper 1, Variant 3
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The following table shows assembly language instructions for a processor that has one general purpose register, the Accumulator (ACC). Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC. LDM #n Immediate addressing. Load the denary number n to ACC. LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC. CMP Compare the contents of ACC with . STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. SUB Subtract the contents of the given address from the contents of ACC. OUT Output to screen the character whose ASCII value is stored in ACC. INC Add 1 to the contents of the register (ACC or . JPE Following a compare instruction, jump to if the compare was True. END Return control to the operating system. The current contents of the main memory are: Address Instruction LDD 200 ADD 201 ADD 202 SUB 203 STO 204 END … Tick (✓) one box to indicate which one of the following statements is true after program execution. Statements Tick (✓) Memory location 204 contains 400 Memory location 204 contains 41 Memory location 204 contains 231 Memory location 204 contains 29 The current contents of the main memory are: Address Instruction LDM #120 ADD 121 SUB 122 STO 120 END … Tick (✓) one box to indicate which one of the following statements is true after program execution. Statement Tick (✓) Memory location 120 contains 135 Memory location 120 contains 118 Memory location 120 contains 0 Memory location 120 contains 16 The current contents of the main memory are: Address Instruction LDI 200 ADD 200 ADD 201 STO 205 END … Tick (✓) one box to indicate which one of the following statements is true after program execution. Statement Tick (✓) Memory location 205 contains 607 Memory location 205 contains 601 Memory location 205 contains 603 Memory location 205 contains 606 Identify two modes of addressing that are not used in parts , or . Assembly language instructions can be put into groups. Tick (✓) one box on each row to indicate the appropriate instruction group for each assembly language instruction. Assembly language instruction Arithmetic Data movement Jump instruction Input and output of data STO 120 JPE 200 ADD 3 LDD 20 INC ACC OUT
9608_w20_qp_11
THEORY
2020
Paper 1, Variant 1
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The fetch-execute cycle is used when a computer processor runs a program. Complete the table by writing the register transfer notation for each of the descriptions. Letter Description Register transfer notation A The Memory Address Register (MAR) stores an address. The contents of this stored address are copied to the Memory Data Register (MDR). B The contents of the Program Counter (PC) are copied to the Memory Address Register (MAR). C The contents of the Memory Data Register (MDR) are copied to the Current Instruction Register (CIR). D The contents of the Program Counter (PC) are incremented. Write one of the letters A, B, C or D (from the table above) on each row (1 to 4), to show the correct order of the fetch-execute cycle. Buses are used to transfer data between various components of the computer system. Tick (✓) one or more boxes on each row to identify the buseach statement describes. Statement Address bus Control bus Data bus Receives data from the MAR Carries an address or an instruction or a value Transmits timing signals to components Bidirectional The following table shows assembly language instructions for a processor that has one general purpose register, the Accumulator (ACC). Instruction Explanation Op code Operand INV Input a denary value from the keyboard and store it in ACC. LDD Direct addressing. Load the contents of the location at the given address to ACC. LDM #n Immediate addressing. Load the denary number n to ACC. LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC. ADD Add the contents of the given address to ACC. OUT Output to screen the character whose ASCII value is stored in ACC. INC Add 1 to the contents of the register (ACC or . CMP Compare the contents of ACC with the contents of . JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. STO Store contents of ACC at the given address. END Return control to the operating system. The assembly language instructions are grouped according to their function. Write one example of an op code from the table of instructions for each of the following groups. Arithmetic Data movement The current contents of the main memory are: Address Instruction INV STO 901 INV STO 900 ADD 902 STO 902 LDD 903 INC ACC STO 903 CMP 901 JPN 502 END … The current contents of a general-purpose register X are: X The contents of X represent an unsigned binary integer. Convert the contents of X into denary. The contents of X represent a two’s complement binary integer. Convert the contents of X into denary. State why the binary number in X cannot represent a Binary Coded Decimal (BCD).
9608_w20_qp_13
THEORY
2020
Paper 1, Variant 3
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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the location at the given address to the ACC LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to the ACC STO Store the contents of the ACC at the given address ADD Add the contents of the given address to the ACC INC Add 1 to the contents of the register (ACC or JMP Jump to the given address The current contents of the main memory are: Address Instruction LDI 160 ADD 153 STO 153 LDD 160 INC ACC STO 160 JMP 130 … …
9608_w21_qp_11
THEORY
2021
Paper 1, Variant 1
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The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op Code Operand LDD Direct addressing. Load the contents of the location at the given address to ACC CMP Compare the contents of ACC with the contents of SUB Subtract the contents of the given address from the ACC INC Add 1 to the contents of the register (ACC or DEC Subtract 1 from the contents of the register (ACC or STO Store contents of ACC at the given address END Return control to the operating system The instructions in the processor’s instruction set can be grouped according to their function. Identify three different instruction groups from the instructions given in the table. Identify one instruction group not given in the table. The following are four special purpose registers used in the processor: • Program Counter (PC) • Memory Data Register (MDR) • Memory Address Register (MAR) • Current Instruction Register (CIR) Describe the purpose of any three registers from the four given. Register 1 Description Register 2 Description Register 3 Description
9608_w21_qp_12
THEORY
2021
Paper 1, Variant 2
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Describe how the following registers are used in the fetch-execute (F-E) cycle: • Current Instruction Register (CIR) • Program Counter (PC) • Memory Data Register (MDR) • Memory Address Register (MAR). Describe the roles carried out by the Arithmetic and Logic Unit (ALU) and the system clock. ALU System clock The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDM #n Immediate addressing. Load the number n to ACC CMP Compare the contents of ACC with the contents of ADD Add the contents of the given address to the ACC INC Add 1 to the contents of the register (ACC or JPE Following a compare instruction, jump to if the compare was True STO Store the contents of ACC at the given address END Return control to the operating system The instructions in the processor’s instruction set can be grouped according to their function. Identify one instruction group for each instruction in the following table. Instruction Instruction group LDM #12 ADD 21 STO 21 CMP 21 JPE 01 Some assemblers scan the assembly language program twice; these are referred to as two-pass assemblers. Complete these two sentences by writing the missing terms. In the first pass the table is generated. In the second pass the program is converted into code.
9608_w21_qp_13
THEORY
2021
Paper 1, Variant 3
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The diagram shows the components and buses found inside a typical Personal Computer (PC). General purpose registers A B C Arithmetic Logic Unit (ALU) F E D Some components and buses only have labels A to F to identify them. For each label, choose the appropriate title from the following list. The title for label D is already given. • Control bus • System clock • Data bus • Control unit • Main memory • Secondary storage A B C D Address bus E F The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand Op code LDM #n 1100 0001 Immediate addressing. Load number n to ACC. LDD 1100 0010 Direct addressing. Load the contents of the given address to ACC. LDV #n 1100 0011 Relative addressing. Move to the address n locations from the address of the current instruction. Load the contents of this address to ACC. STO 1100 0100 Store the contents of ACC at the given address. DEC 1100 0101 Decrement the contents of ACC. OUTCH 1100 0111 Output the character corresponding to the ASCII character code in ACC. JNE 1110 0110 Following a compare instruction, jump to if the compare was False. JMP 1110 0011 (Unconditionally) jump to the given address. CMP #n 1110 0100 Compare the contents of ACC with number n. The program given in part is to be translated using a two-pass assembler. The program has been copied here for you. The program now starts with a directive which tells the assembler to load the first instruction of the program to address 100. Label ORG #0100 StartProg: LDV #CountDown CMP Num1 JNE CarryOn JMP Finish CarryOn: OUTCH LDD CountDown DEC STO CountDown JMP StartProg Finish: LDM #88 OUTCH END CountDown: Num1: On the first pass of the two-pass process, the assembler adds entries to a symbol table. The following symbol table shows the first eleven entries, part way through the first pass. The circular labels show the order in which the assembler made the entries to the symbol table. Symbol table Symbolic address Absolute address StartProg CountDown UNKNOWN Num1 UNKNOWN CarryOn UNKNOWN 104 11 Finish UNKNOWN Explain how the assembler made these entries to the symbol table. The assembler software must then complete the second pass building up the executable file. Name the second table needed when the assembler software carries out the second pass. The following shows two of the program instructions in machine code. Machine code Instruction Binary Hexadecimal OUTCH 1100 0111 C7 JNE CarryOn A B Each of the numbers A and B represents the complete instruction in two bytes, one byte for the op code and one byte for the operand. Use the following instruction set to write the numbers for A and B. A B Instruction Explanation Op code Operand Op code LDM #n 1100 0001 Immediate addressing. Load number n to ACC. LDD 1100 0010 Direct addressing. Load the contents of the given address to ACC. LDV #n 1100 0011 Relative addressing. Move to the address n locations from the address of the current instruction. Load the contents of this address to ACC. STO 1100 0100 Store the contents of ACC at the given address. DEC 1100 0101 Decrement the contents of ACC. OUTCH 1100 0111 Output the character corresponding to the ASCII character code in ACC. JNE 1110 0110 Following a compare instruction, jump to if the compare was False. JMP 1110 0011 (Unconditionally) jump to the given address. CMP #n 1110 0100 Compare the contents of ACC with number n.
9608_w17_qp_11
THEORY
2017
Paper 1, Variant 1
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Questions Discovered
63