The following diagram shows the components and buses found inside a typical personal computer (PC). A B C Control unit Main memory F E D Some components and buses only have labels A to F to identify them. For each label, choose the appropriate title from the following list. The title for label D is already given. • Control bus • Address bus • Arithmetic Logic Unit (ALU) • General purpose registers • Secondary storage • System clock A B C D Data bus E F Clock speed is a factor that affects the performance of a PC. Explain this statement. An assembly language program can contain both macros and directives. Explain what is meant by these terms. Macro Directive Give an example of the use of a directive. The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDD Direct addressing. Load the contents of the given address to ACC. LDV #n Relative addressing. Move to the address n locations from the address of the current instruction. Load the contents of this address to ACC. STO Store the contents of ACC at the given address. INC Increment the contents of ACC. OUTCH Output the character corresponding to the ASCII character code in ACC. JPE Following a compare instruction, jump to if the compare was True. JMP Jump to the given address. CMP #n Compare the contents of ACC with number n. The program given in part is to be translated using a two-pass assembler. The program has been copied here for you. Label Instruction StartProg: LDV #Offset CMP Value JPE EndProg OUTCH LDD Offset INC STO Offset JMP StartProg EndProg: END Offset: Value: On the first pass, the assembly process adds entries to a symbol table. The following symbol table shows the first five entries, part way through the first pass. The circular labels show the order in which the assembler made the entries to the symbol table. Complete the symbol table. Use circular labels to show the order in which the assembler makes the entries. Symbol table Symbolic address Relative address StartProg Offset UNKNOWN Value

9608_w17_qp_12

THEORY

2017

Paper 1, Variant 2

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The diagram shows the components and buses found inside a typical Personal Computer (PC). General purpose registers A B C Arithmetic Logic Unit (ALU) F E D Some components and buses only have labels A to F to identify them. For each label, choose the appropriate title from the following list. The title for label D is already given. • Control bus • System clock • Data bus • Control unit • Main memory • Secondary storage A B C D Address bus E F The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand Op code LDM #n 1100 0001 Immediate addressing. Load number n to ACC. LDD 1100 0010 Direct addressing. Load the contents of the given address to ACC. LDV #n 1100 0011 Relative addressing. Move to the address n locations from the address of the current instruction. Load the contents of this address to ACC. STO 1100 0100 Store the contents of ACC at the given address. DEC 1100 0101 Decrement the contents of ACC. OUTCH 1100 0111 Output the character corresponding to the ASCII character code in ACC. JNE 1110 0110 Following a compare instruction, jump to if the compare was False. JMP 1110 0011 (Unconditionally) jump to the given address. CMP #n 1110 0100 Compare the contents of ACC with number n. The program given in part is to be translated using a two-pass assembler. The program has been copied here for you. The program now starts with a directive which tells the assembler to load the first instruction of the program to address 100. Label ORG #0100 StartProg: LDV #CountDown CMP Num1 JNE CarryOn JMP Finish CarryOn: OUTCH LDD CountDown DEC STO CountDown JMP StartProg Finish: LDM #88 OUTCH END CountDown: Num1: On the first pass of the two-pass process, the assembler adds entries to a symbol table. The following symbol table shows the first eleven entries, part way through the first pass. The circular labels show the order in which the assembler made the entries to the symbol table. Symbol table Symbolic address Absolute address StartProg CountDown UNKNOWN Num1 UNKNOWN CarryOn UNKNOWN 104 11 Finish UNKNOWN Explain how the assembler made these entries to the symbol table. The assembler software must then complete the second pass building up the executable file. Name the second table needed when the assembler software carries out the second pass. The following shows two of the program instructions in machine code. Machine code Instruction Binary Hexadecimal OUTCH 1100 0111 C7 JNE CarryOn A B Each of the numbers A and B represents the complete instruction in two bytes, one byte for the op code and one byte for the operand. Use the following instruction set to write the numbers for A and B. A B Instruction Explanation Op code Operand Op code LDM #n 1100 0001 Immediate addressing. Load number n to ACC. LDD 1100 0010 Direct addressing. Load the contents of the given address to ACC. LDV #n 1100 0011 Relative addressing. Move to the address n locations from the address of the current instruction. Load the contents of this address to ACC. STO 1100 0100 Store the contents of ACC at the given address. DEC 1100 0101 Decrement the contents of ACC. OUTCH 1100 0111 Output the character corresponding to the ASCII character code in ACC. JNE 1110 0110 Following a compare instruction, jump to if the compare was False. JMP 1110 0011 (Unconditionally) jump to the given address. CMP #n 1110 0100 Compare the contents of ACC with number n.

9608_w17_qp_13

THEORY

2017

Paper 1, Variant 3

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A student has written the steps of the fetch stage of the fetch-execute (FE) cycle in register transfer notation. The student has made some errors. Line 1 MDR Line 2 PC PC + 1 Line 3 MDR Line 4 CIR PC Identify the line numbers of three errors that the student has made. Write the correct notation for each error. Line number of error Correct notation One stage of the FE cycle includes checking for interrupts. Give three different events that can generate an interrupt. Explain how interrupts are handled during the fetch-execute cycle. The processor uses buses in the FE cycle. The diagram shows three buses and two descriptions. Draw one line from each bus to its appropriate description. Bus Description Control bus Address bus Data bus Unidirectional (one direction) Bidirectional (two directions)

9608_w18_qp_12

THEORY

2018

Paper 1, Variant 2

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A simple program written in assembly language is translated using a two-pass assembler. The table contains some of the tasks performed by a two-pass assembler. Tick (✓) one box in each row to indicate whether the task is performed at the first or second pass. The first row has been completed for you. Task First pass Second pass Creation of symbol table ✓ Expansion of macros Generation of object code Removal of comments The processor’s instruction set can be grouped according to their function. For example, one group is modes of addressing. Identify two other groups of instructions. The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDM #n Immediate addressing. Load the denary number n to ACC. LDD Direct addressing. Load the contents of the location at the given address to ACC. LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC. LDR #n Immediate addressing. Load the denary number n to IX. STO Store contents of ACC at the given address. ADD Add the contents of the given address to ACC. INC Add 1 to the contents of the register (ACC or . CMP #n Compare contents of ACC with denary number n. JPE Following a compare instruction, jump to if the compare was True. JPN Following a compare instruction, jump to if the compare was False. JMP Jump to the given address. OUT Output to screen the character whose ASCII value is stored in ACC. END Return control to the operating system. The current contents of the main memory, Index Register (and selected values from the ASCII character set are: Address Instruction LDM #0 STO 300 CMP #0 JPE 28 LDX 100 ADD 301 OUT JMP 30 LDX 100 OUT LDD 300 INC ACC STO 300 INC IX CMP #2 JPN 22 END … … IX ASCII code table (Selected codes only) ASCII Code Character A B C D E a b c d e

9608_s19_qp_11

THEORY

2019

Paper 1, Variant 1

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The steps 1 to 6 describe the first pass of a two‑pass assembler. The following three statements are used to complete the sequence of steps. A If it is already in the symbol table, it checks to see if the absolute address is known B When it meets a symbolic address, it checks to see if it is already in the symbol table C If it is known, it is entered Write one of the letters A, B or C in the appropriate step to complete the sequence. 1. The assembler reads the assembly language instructions 2. 3. If it is not, it adds it to the symbol table 4. 5. 6. If it is not known, it is marked as unknown. The assembler translates assembly code into machine code. The table shows the denary values for three assembler op codes. Op code Denary value LDD ADD STO Convert the denary value for the op code LDD into 8‑bit binary. Convert the denary value for the op code STO into hexadecimal. State why the denary value for the op code ADD cannot be represented in 8‑bit two’s complement form. Justify your answer. The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Op code Operand LDM #n Immediate addressing. Load the denary number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC LDX Indexed addressing. Form the address from + the contents of the Index Register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the denary number n to IX STO Store contents of ACC at the given address ADD Add the contents of the given address to ACC INC Add 1 to the contents of the register (ACC or CMP Compare contents of the address given with the contents of ACC JPE Following a compare instruction, jump to if the compare was True JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address OUT Output to screen the character whose ASCII value is stored in ACC END Return control to the operating system

9608_s20_qp_12

THEORY

2020

Paper 1, Variant 2

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A program is written in assembly language. The op codes LDM and LDD are used to load a register. The op code LDM uses immediate addressing, and the op code LDD uses direct addressing. Describe what happens when the following instructions are run. LDM #300 LDD 300 Assembly language instructions can be grouped by their purpose. The following table shows four assembly language instructions. Tick (✓) one box in each row to indicate the group each instruction belongs to. Instruction Description Jump instruction Arithmetic operation Data movement LDR #3 Load the number 3 to the Index Register ADD #2 Add 2 to the Accumulator JPN 22 Move to the instruction at address 22 DEC ACC Subtract 1 from the Accumulator The processor handles interrupts within the fetch-execute cycle. Give one example of a hardware interrupt and one example of a software interrupt. Hardware Software Explain how the processor handles an interrupt.

9608_s19_qp_13

THEORY

2019

Paper 1, Variant 3

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Assemblers translate from assembly language to machine code. Some assemblers scan the assembly language program twice; these are referred to as two-pass assemblers. The following table shows five activities performed by two-pass assemblers. Write 1 or 2 to indicate whether the activity is carried out during the first pass or during the second pass. Activity First pass or second pass any symbolic address is replaced by an absolute address any directives are acted upon any symbolic address is added to the symbolic address table data items are converted into their binary equivalent forward references are resolved

9608_s15_qp_13

THEORY

2015

Paper 1, Variant 3

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An intruder detection system for a large house has four sensors. An 8-bit memory location stores the output from each sensor in its own bit position. The bit value for each sensor shows: • 1 – the sensor has been triggered • 0 – the sensor has not been triggered The bit positions are used as follows: Not used Sensor 4 Sensor 3 Sensor 2 Sensor 1 The output from the intruder detection system is a loud alarm. State the name of the type of system to which intruder detection systems belong. Justify your answer to part . Name two sensors that could be used in this intruder detection system. Give a reason for your choice. Sensor 1 Reason Sensor 2 Reason Part of the assembly code is: Op code Operand SENSORS: B00001010 COUNT: VALUE: LOOP: LDD SENSORS AND VALUE CMP #0 JPE ZERO LDD COUNT INC ACC STO COUNT ZERO: LDD VALUE CMP #8 JPE EXIT ADD VALUE STO VALUE JMP LOOP EXIT: LDD COUNT TEST: CMP … JGT ALARM Dry run the assembly language code. Start at LOOP and finish when EXIT is reached. BITREG COUNT VALUE ACC B00001010 The operand for the instruction labelled TEST is missing. State the missing operand. The intruder detection system is improved and now has eight sensors. One instruction in the assembly language code will need to be amended. Identify this instruction Write the amended instruction

9608_s16_qp_31

THEORY

2016

Paper 3, Variant 1

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An intruder detection system for a large house has four sensors. An 8-bit memory location stores the output from each sensor in its own bit position. The bit value for each sensor shows: • 1 – the sensor has been triggered • 0 – the sensor has not been triggered The bit positions are used as follows: Not used Sensor 4 Sensor 3 Sensor 2 Sensor 1 The output from the intruder detection system is a loud alarm. State the name of the type of system to which intruder detection systems belong. Justify your answer to part . Name two sensors that could be used in this intruder detection system. Give a reason for your choice. Sensor 1 Reason Sensor 2 Reason Part of the assembly code is: Op code Operand SENSORS: B00001010 COUNT: VALUE: LOOP: LDD SENSORS AND VALUE CMP #0 JPE ZERO LDD COUNT INC ACC STO COUNT ZERO: LDD VALUE CMP #8 JPE EXIT ADD VALUE STO VALUE JMP LOOP EXIT: LDD COUNT TEST: CMP … JGT ALARM Dry run the assembly language code. Start at LOOP and finish when EXIT is reached. BITREG COUNT VALUE ACC B00001010 The operand for the instruction labelled TEST is missing. State the missing operand. The intruder detection system is improved and now has eight sensors. One instruction in the assembly language code will need to be amended. Identify this instruction Write the amended instruction

9608_s16_qp_32

THEORY

2016

Paper 3, Variant 2

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An intruder detection system for a large house has four sensors. An 8-bit memory location stores the output from each sensor in its own bit position. The bit value for each sensor shows: • 1 – the sensor has been triggered • 0 – the sensor has not been triggered The bit positions are used as follows: Not used Sensor 4 Sensor 3 Sensor 2 Sensor 1 The output from the intruder detection system is a loud alarm. State the name of the type of system to which intruder detection systems belong. Justify your answer to part . Name two sensors that could be used in this intruder detection system. Give a reason for your choice. Sensor 1 Reason Sensor 2 Reason Part of the assembly code is: Op code Operand SENSORS: B00001010 COUNT: VALUE: LOOP: LDD SENSORS AND VALUE CMP #0 JPE ZERO LDD COUNT INC ACC STO COUNT ZERO: LDD VALUE CMP #8 JPE EXIT ADD VALUE STO VALUE JMP LOOP EXIT: LDD COUNT TEST: CMP … JGT ALARM Dry run the assembly language code. Start at LOOP and finish when EXIT is reached. BITREG COUNT VALUE ACC B00001010 The operand for the instruction labelled TEST is missing. State the missing operand. The intruder detection system is improved and now has eight sensors. One instruction in the assembly language code will need to be amended. Identify this instruction Write the amended instruction

9608_s16_qp_33

THEORY

2016

Paper 3, Variant 3

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