15.1. Processors, Parallel Processing and Virtual Machines
A subsection of Computer Science, 9618, through 15. Hardware and Virtual Machines
Listing 10 of 11 questions
Describe the use of pipelining in Reduced Instruction Set Computers (RISC). The processing of instructions is divided into five stages: • instruction fetch (IF) • instruction decode (ID) • operand fetch (OF) • instruction execute (IE) • write back result (WB) Each stage is carried out using a different register when pipelining is used. Complete the table to show how a program consisting of six instructions would be completed using pipelining. Clock cycles Processor stages IF ID OF IE WB
9618_s23_qp_32
THEORY
2023
Paper 3, Variant 2
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Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) are two types of processor. Tick (3) one box in each row to show if the statement applies to RISC or CISC processors. Statement RISC CISC uses a smaller instruction set uses single-cycle instructions and limited addressing modes uses fewer general-purpose registers uses both hardwired and micro-coded control unit uses a system where cache is split between data and instructions Describe the process of pipelining during the fetch-execute cycle in RISC processors.
9618_w22_qp_31
THEORY
2022
Paper 3, Variant 1
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Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) are two types of processor. Tick (3) one box in each row to show if the statement applies to RISC or CISC processors. Statement RISC CISC uses a smaller instruction set uses single-cycle instructions and limited addressing modes uses fewer general-purpose registers uses both hardwired and micro-coded control unit uses a system where cache is split between data and instructions Describe the process of pipelining during the fetch-execute cycle in RISC processors.
9618_w22_qp_33
THEORY
2022
Paper 3, Variant 3
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Questions Discovered
11