3.1. Computer architecture
A subsection of Computer Science, 0478, through 3. Hardware
Listing 10 of 56 questions
The Von Neumann model for a computer system uses components, such as registers and buses, in the fetch-execute cycle. Draw a line to connect each component to its correct description. Component Description Control Bus Increments to point to the address of the next instruction to be fetched Program Counter (PC) Holds the result of a calculation. It is located within the Arithmetic Logic Unit (ALU) Memory Data Register (MDR) Carries signals to synchronise the fetch-execute cycle Accumulator (ACC) Temporary storage between the Central Processing Unit (CPU) and primary memory State two buses, other than the control bus, used in the Von Neumann model for a computer system.
0478_m20_qp_12
THEORY
2020
Paper 1, Variant 2
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One of the key features of von Neumann computer architecture is the use of buses. Three buses and three descriptions are shown below. Draw a line to connect each bus to its correct description. Bus Description address bus this bus carries signals used to coordinate the computer’s activities control bus this bi-directional bus is used to exchange data between processor, memory and input/ output devices data bus this uni-directional bus carries signals relating to memory addresses between processor and memory The seven stages in a von Neumann fetch-execute cycle are shown in the table below. Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand column. The first one has been done for you. Stage Sequence number the instruction is then copied from the memory location contained in the MAR (memory address register) and is placed in the MDR (memory data register) the instruction is finally decoded and is then executed the PC (program counter) contains the address of the next instruction to be fetched the entire instruction is then copied from the MDR (memory data register) and placed in the CIR (current instruction register) the address contained in the PC (program counter) is copied to the MAR (memory address register) via the address bus the address part of the instruction, if any, is placed in the MAR (memory address register) the value in the PC (program counter) is then incremented so that it points to the next instruction to be fetched
0478_s15_qp_11
THEORY
2015
Paper 1, Variant 1
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One of the key features of von Neumann computer architecture is the use of buses. Three buses and three descriptions are shown below. Draw a line to connect each bus to its correct description. Bus Description address bus this bus carries signals used to coordinate the computer’s activities control bus this bi-directional bus is used to exchange data between processor, memory and input/ output devices data bus this uni-directional bus carries signals relating to memory addresses between processor and memory The seven stages in a von Neumann fetch-execute cycle are shown in the table below. Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand column. The first one has been done for you. Stage Sequence number the instruction is then copied from the memory location contained in the MAR (memory address register) and is placed in the MDR (memory data register) the instruction is finally decoded and is then executed the PC (program counter) contains the address of the next instruction to be fetched the entire instruction is then copied from the MDR (memory data register) and placed in the CIR (current instruction register) the address contained in the PC (program counter) is copied to the MAR (memory address register) via the address bus the address part of the instruction, if any, is placed in the MAR (memory address register) the value in the PC (program counter) is then incremented so that it points to the next instruction to be fetched
0478_s15_qp_13
THEORY
2015
Paper 1, Variant 3
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Six components of the Von Neumann model for a computer system and six descriptions are given. Draw a line to match each component to the most suitable description. Component Immediate access store (IAS) Register Accumulator (ACC) Bus Control unit (CU) Arithmetic logic unit (ALU) Description Holds data and instructions when they are loaded from main memory and are waiting to be processed. Holds data temporarily that is currently being used in a calculation. Manages the flow of data and interaction between the components of the processor. Pathway for transmitting data and instructions. Holds data or instructions temporarily when they are being processed. Carries out the calculations on data.
0478_s18_qp_11
THEORY
2018
Paper 1, Variant 1
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Kelvin correctly answers an examination question about the Von Neumann model. Eight different terms have been removed from his answer. Complete the sentences in Kelvin’s answer, using the list given. Not all items in the list need to be used. • accumulator (ACC) • address bus • arithmetic logic unit (ALU) • control unit (CU) • data bus • executed • fetches • immediate access store (IAS) • memory address register (MAR) • memory data register (MDR) • program counter (PC) • saved • transmits The central processing unit (CPU) the data and instructions needed and stores them in the to wait to be processed. The holds the address of the next instruction. This address is sent to the . The data from this address is sent to the . The instruction can then be decoded and . Any calculations that are carried out on the data are done by the . During calculations, the data is temporarily held in a register called the .
0478_s18_qp_12
THEORY
2018
Paper 1, Variant 2
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Vanessa writes a paragraph as an answer to an examination question about the central processing unit (CPU). Use the list given to complete Vanessa’s answer by inserting the correct six missing terms. Not all terms will be used. • Components • Data • Decoded • Executed • Fetched • Instructions • RAM • ROM • Secondary storage The CPU processes and . An instruction is from into the CPU where it is then . Once this has taken place the instruction is then .
0478_s19_qp_12
THEORY
2019
Paper 1, Variant 2
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A clothing shop uses a barcode reader at the checkout. The checkout is linked to a stock control system. The system monitors stock levels and automatically keeps them above a minimum level. Explain how the stock control system automatically keeps the stock levels above a minimum level. The software for the stock control system is stored on a central computer. The computer uses random access memory (RAM), read only memory (ROM) and a hard disk drive (HDD). The computer is a Von Neumann model computer system with a central processing unit (CPU). State the purpose of the RAM, ROM and HDD in the central computer. RAM ROM HDD Identify four components that are part of the CPU. Component 1 Component 2 Component 3 Component 4
0478_s20_qp_13
THEORY
2020
Paper 1, Variant 3
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Questions Discovered
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