4. Processor Fundamentals
A section of Computer Science, 9618
Listing 10 of 16 questions
A computer system is designed using the basic Von Neumann model. Describe the role of the registers in the Fetch-Execute (F-E) cycle. Describe when interrupts are detected in the F-E cycle and how the interrupts are handled. Detected Handled Identify one factor that can affect the performance of the computer system and state how it impacts the performance. Factor Impact Question 6 continues on the next page. The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC). Instruction Explanation Opcode Operand AND #n Bitwise AND operation of the contents of ACC with the operand XOR #n Bitwise XOR operation of the contents of ACC with the operand OR #n Bitwise OR operation of the contents of ACC with the operand LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end # denotes a denary number, e.g. #123 Complete the register to show the result after the instruction AND #2 is executed. Register before: Register after: Complete the register to show the result after the instruction OR #8 is executed. Register before: Register after: Complete the register to show the result after the operation LSL #4 is executed. Register before: Register after:
9618_s22_qp_11
THEORY
2022
Paper 1, Variant 1
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A student has purchased a new laptop. The laptop is designed using the Von Neumann model for a computer system. Identify two types of signal that a control bus can transfer. Describe two ways the hardware of a laptop can be upgraded to improve the performance and explain how each upgrade improves the performance. Peripherals are connected to the laptop using ports. A printer is connected to a Universal Serial Bus (USB) port. Describe how data is transmitted through a USB port. A monitor is connected to the laptop using a different type of port. Identify one other type of port that can be used to connect the monitor. The laptop has systems software. Describe how the Operating System (OS) manages processes in the computer. Describe the purpose of utility software in a computer.
9618_s23_qp_12
THEORY
2023
Paper 1, Variant 2
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A computer stores data in binary form. Draw one line from each description to its matching denary value. Description Denary value The smallest integer that can be represented in 8-bit two’s complement. The largest integer that can be represented in 8-bit two’s complement. The largest unsigned integer that can be represented in 8 bits. −255 −128 −256 −127 The computer has a Control Unit (CU), system clock and control bus. Explain how the CU, system clock and control bus operate to transfer data between the components of the computer system. Complete the table by writing the register transfer notation for each stage of the Fetch-Execute (F-E) cycle given in the table. Stage description Register transfer notation The Program Counter (PC) is incremented The data in the address stored in the Memory Address Register (MAR) is copied to the Memory Data Register (MDR)
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THEORY
2023
Paper 1, Variant 3
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The Von Neumann model for a computer system uses registers. Describe the role of the following special purpose registers in the fetch-execute (F-E) cycle. Memory Address Register (MAR) Memory Data Register (MDR) Another special purpose register is the Index Register. Identify one other special purpose register used in the Von Neumann model for a computer system. The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC STO Store the contents of ACC at the given address INC Add 1 to the contents of the register (ACC or CMP Compare the contents of ACC with the contents of JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address IN Key in a character and store its ASCII value in ACC OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 The current contents of main memory are shown: Address Data In the following table, each row shows the current contents of the ACC in binary and the instruction that will be performed on those contents. Complete the table by writing the new contents of the ACC after the execution of each instruction. Current contents of the ACC Instruction New contents of the ACC XOR 101 AND 104 LSL #4 OR 102 The following table contains five assembly language instruction groups. Write an appropriate assembly language instruction for each instruction group, using the given instruction set. The first one has been completed for you. Instruction Group Instruction Data movement LDM #2 Input and output of data Arithmetic operations Unconditional and conditional instructions Compare instructions The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing. Identify and describe one additional mode of addressing. Mode of addressing Description
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THEORY
2021
Paper 1, Variant 2
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A Central Processing Unit (CPU) contains several special purpose registers and other components. State the roles of the following registers. Memory Address Register (MAR) Memory Data Register (MDR) State when interrupts are detected during the Fetch-Execute (F-E) cycle. A computer system contains a system clock. Describe the purpose of the system clock. Upgrading secondary storage to solid state typically improves the performance of computer systems. Identify one other upgrade to the hardware and explain why it improves the performance of a computer system. Upgrade Explanation
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THEORY
2022
Paper 1, Variant 3
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The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC). Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC LDI Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC can be an absolute or symbolic address # denotes a denary number, e.g. #123 The current contents of main memory are: Address Complete the table by writing the value stored in the accumulator after the execution of each instruction. Instruction Accumulator LDM #103 LDD 102 LDI 103 The instructions in part are examples of the data movement group. Describe two other instruction groups. The table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC). Instruction Explanation Opcode Operand AND Bn Bitwise AND operation of the contents of ACC with the operand XOR Bn Bitwise XOR operation of the contents of ACC with the operand OR Bn Bitwise OR operation of the contents of ACC with the operand B denotes a binary number, e.g. B01001010 The binary value 00111101 is stored in the memory address 200. Each instruction in the diagram is performed on the data in memory address 200. Draw one line from each instruction to its correct result. Instruction Result XOR B11110000 OR B01010101 AND B11111111
9618_s22_qp_13
THEORY
2022
Paper 1, Variant 3
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There are two errors in the following register transfer notation for the fetch‑execute cycle. MAR PC − 1 MDR CIR Complete the following table by: • identifying the line number of each error • describing the error • writing the correct statement. Line number Description of the error Correct statement The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC STO Store the contents of ACC at the given address INC Add 1 to the contents of the register (ACC or CMP Compare the contents of ACC with the contents of JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address IN Key in a character and store its ASCII value in ACC OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The current contents of main memory are shown: Address Data
9618_w21_qp_11
THEORY
2021
Paper 1, Variant 1
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There are two errors in the following register transfer notation for the fetch‑execute cycle. MAR PC − 1 MDR CIR Complete the following table by: • identifying the line number of each error • describing the error • writing the correct statement. Line number Description of the error Correct statement The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (. Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD Direct addressing. Load the contents of the location at the given address to ACC STO Store the contents of ACC at the given address INC Add 1 to the contents of the register (ACC or CMP Compare the contents of ACC with the contents of JPN Following a compare instruction, jump to if the compare was False JMP Jump to the given address IN Key in a character and store its ASCII value in ACC OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system XOR #n Bitwise XOR operation of the contents of ACC with the operand XOR Bitwise XOR operation of the contents of ACC with the contents of AND #n Bitwise AND operation of the contents of ACC with the operand AND Bitwise AND operation of the contents of ACC with the contents of OR #n Bitwise OR operation of the contents of ACC with the operand OR Bitwise OR operation of the contents of ACC with the contents of LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end can be an absolute or symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101 The current contents of main memory are shown: Address Data
9618_w21_qp_13
THEORY
2021
Paper 1, Variant 3
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Questions Discovered
16